The Instruction set below can be downloaded in Word format from the Crib Sheets page.
|
Instruction |
Syntax |
Description |
|
ABCD |
ABCD Dy,Dx ABCD -(Ay),-(Ax) |
Add the source operand to the destination operand along with the extend bit, and store the result in the destination location |
|
ADD |
ADD <ea>,Dn ADD Dn,<ea> |
Add the source operand to the destination operand and store the result in the destination location. |
|
ADDA |
ADDA <ea>,An |
Add the source operand to the destination address register and store the result in the destination address register. |
|
ADDI |
ADDI #,<ea> |
Add immediate data to the destination operand. Store the result in the destination operand. |
|
ADDQ |
ADDQ #,<ea> |
Add the immediate data to the contents of the destination operand. |
|
ADDX |
ADDX Dy,Dx ADDX -(Ay),-(Ax) |
Add the source operand to the destination operand along with the extend bit, and store the result in the destination location. |
|
AND |
AND <ea>,Dn AND Dn,<ea> |
AND the source operand to the destination operand and store the result in the destination location. |
|
ANDI |
ANDI #,<ea> |
AND the immediate data to the destination operand. |
|
ANDI-CCR |
ANDI #,CCR |
AND the immediate data to the condition code register (the least-significant byte of the status register). |
|
ANDI-SR |
ANDI #,SR |
AND the immediate data to the status register and store the result in the status register. |
|
ASL |
ASL Dx,Dy ASL #,Dy ASL <ea> |
Arithmetically shift left the bits of the operand. |
|
ASR |
ASR Dx,Dy ASR #,Dy ASR <ea> |
Arithmetically shift right the bits of the operand. |
|
Bcc |
BEQ <label> |
If the specified logical condition is met, program execution continues at location [PC] + displacement, d |
|
BCHG |
BCHG Dn,<ea> BCHG #,<ea> |
A bit in the destination operand is tested and the state of the specified bit is reflected in the condition of the Z-bit in the CCR. |
|
BCLR |
BCLR Dn,<ea> BCLR #,<ea> |
A bit in the destination operand is tested and the state of the specified bit is reflected in the condition of the Z-bit in the condition code. |
|
BRA |
BRA <label> BRA <literal> |
Program execution continues at location [PC] + d. |
|
BSET |
BSET Dn,<ea> BSET #,<ea> |
A bit in the destination operand is tested and the state of the specified bit is reflected in the condition of the Z-bit of the condition code. |
|
BSR |
BSR <label> BSR <literal> |
The longword address of the instruction immediately following the BSR instruction is pushed onto the system stack pointed at by A7. |
|
BTST |
BTST Dn,<ea> BTST #,<ea> |
A bit in the destination operand is tested and the state of the specified bit is reflected in the condition of the Z-bit in the CCR. |
|
CHK |
CHK <ea>,Dn |
The contents of the low-order word in the data register specified in the instruction are examined and compared with the upper bound at the effective address. |
|
CLR |
CLR <ea> |
The destination is cleared . loaded with all zeros. |
|
CMP |
CMP <ea>,Dn |
Subtract the source operand from the destination operand and set the condition codes accordingly. |
|
CMPA |
CMPA <ea>,An |
Subtract the source operand from the destination address register and set the condition codes accordingly. |
|
CMPI |
CMPI #,<ea> |
Subtract the immediate data from the destination operand and set the condition codes accordingly . |
|
CMPM |
CMPM (Ay)+,(Ax)+ |
Subtract the source operand from the destination operand and set the condition codes accordingly. |
|
DBcc |
DBcc Dn,<label> |
The DBcc instruction provides an automatic looping facility and replaces the usual decrement counter, test, and branch instructions. |
|
DIVS |
DIVS <ea>,Dn |
Divide the destination operand by the source operand and store the result in the destination. (signed) |
|
DIVU |
DIVU <ea>,Dn |
Divide the destination operand by the source operand and store the result in the destination. (unsigned) |
|
EOR |
EOR Dn,<ea> |
EOR (exclusive or) the source operand with the destination operand and store the result in the destination location. |
|
EORI |
EORI #,<ea> |
EOR the immediate data with the contents of the destination operand. |
|
EORI-CCR |
EORI #,CCR |
EOR the immediate data with the contents of the condition code register (the least-significant byte of the status register). |
|
EORI-SR |
EORI #,SR |
EOR (exclusive OR) the immediate data with the contents of the status register and store the result in the status register. |
|
EXG |
EXG Rx,Ry |
Exchange the contents of two registers. |
|
ExT |
EXT.W Dn EXT.L Dn |
Extend the least-significant byte in a data register to a word, or extend the least-significant word in a data register to a longword. |
|
ILLEGAL |
ILLEGAL |
The bit pattern of the illegal instruction, 4AFC16 causes the illegal instruction trap to be taken. The contents of the program counter and the processor status word are pushed onto the supervisor stack at the start of exception processing. |
|
JMP |
JMP <ea> |
Program execution continues at the effective address specified by the instruction. |
|
JSR |
JSR <ea> |
The longword address of the instruction immediately following the JSR is pushed onto the system stack. Program execution then continues at the address specified in the instruction. |
|
LEA |
LEA <ea>,An |
The effective address is computed and loaded into the specified address register. |
|
LINK |
LINK An,#<disp> |
The contents of the specified address register are first pushed onto the stack. The address register is loaded with the updated stack pointer and the 16-bit sign-extended displacement is added to the stack pointer. |
|
LSL |
LSL Dx,Dy LSL #,Dy LSL <ea> |
Logically shift left the bits of the operand.
|
|
LSR |
LSR Dx,Dy LSR #,Dy LSR <ea> |
Logically shift right the bits of the operand. |
|
MOVE |
MOVE <ea>,<e> |
Move the contents of the source to the destination location. |
|
MOVEA |
MOVEA <ea>,An |
Move the contents of the source to the destination location. The destination is an address register. |
|
MOVE-CCR |
MOVE <ea>,CCR |
Move the contents of the source operand to the condition code register. |
|
MOVE-SR |
MOVE SR,<ea> MOVE <ea>,SR |
Move the contents of the status register to the destination location or vice versa. |
|
MOVE USP |
MOVE USP,An MOVE An,USP |
Move the contents of the user stack pointer to an address register or vice versa. |
|
MOVEM |
MOVEM <ea>,<reglist> MOVEM <reglist>,<ea> |
The group of registers specified by <reglist> is copied to or from consecutive memory locations. |
|
MOVEP |
MOVEP D3,(Control,A0) MOVEP (Input,A6),D5 |
Move data between a data register and a byte-oriented memory mapped peripheral. |
|
MOVEQ |
MOVEQ #,Dn |
Move the specified literal to a data register. |
|
MULS |
MULS <ea>,Dn |
Multiply the 16-bit destination operand by the 16-bit source operand and store the result in the destination (signed). |
|
MULU |
MULU <ea>,Dn |
Multiply the 16-bit destination operand by the 16-bit source operand and store the result in the destination (unsigned). |
|
NBCD |
NBCD <ea> |
The operand addressed as the destination and the extend bit in the CCR are subtracted from zero. |
|
NEG |
NEG <ea> |
Subtract the destination operand from 0 and store the result in the destination location. |
|
NEGX |
NEGX <ea> |
The operand addressed as the destination and the extend bit are subtracted from zero. |
|
NOP |
NOP |
The no operation instruction. |
|
NOT |
NOT <ea> |
Calculate the logical complement of the destination and store the result in the destination. |
|
OR |
OR <ea>,Dn OR Dn,<ea> |
OR the source operand to the destination operand, and store the result in the destination location. |
|
ORI |
ORI #,<ea> |
OR the immediate data with the destination operand. Store the result in the destination operand. |
|
ORI-CCR |
ORI #,CCR |
OR the immediate data with the condition code register. |
|
ORI-SR |
ORI #,SR |
OR the immediate data to the status register and store the result in the status register. |
|
PEA |
PEA <ea> |
The longword effective address specified by the instruction is computed and pushed onto the stack. |
|
RESET |
RESET |
The reset line is asserted, causing all external devices connected to the 68000.s RESET* output to be reset. |
|
ROL |
ROL Dx,Dy ROL #,Dy ROL <ea> |
Rotate the bits of the operand left. |
|
ROR |
ROR Dx,Dy ROR #,Dy ROR <ea> |
Rotate the bits of the operand right. |
|
ROXL |
ROXL Dx,Dy ROXL #,Dy ROXL <ea>
|
Rotate the bits of the operand left. The extend bit of the CCR is included in the rotation. |
|
ROXR |
ROXR Dx,Dy ROXR #,Dy ROXR <ea> |
Rotate the bits of the operand right. The extend bit of the CCR is included in the rotation. |
|
RTE |
RTE |
The status register and program counter are pulled from the stack. |
|
RTR |
RTR |
The condition code and program counter are pulled from the stack. |
|
RTS |
RTS |
The program counter is pulled from the stack and the previous value of the PC is lost. |
|
SBCD |
SBCD Dy,Dx SBCD -(Ay),-(Ax) |
Subtract the source operand from the destination operand together with the X-bit, and store the result in the destination. |
|
Scc |
Scc <ea> |
The specified condition code is tested. If the condition is true, the bits at the effective address are all set to one |
|
STOP |
STOP # |
The immediate operand is copied into the entire status register and the PC is advanced to point to the next instruction to be executed. |
|
SUB |
SUB <ea>,Dn SUB Dn,<ea> |
Subtract the source operand from the destination operand and store the result in the destination location. |
|
SUBA |
SUBA <ea>,An |
Subtract the source operand from the destination operand and store the result in the destination address register. |
|
SUBI |
SUBI #,<ea> |
Subtract the immediate data from the destination operand. Store the result in the destination operand. |
|
SUBQ |
SUBQ #,<ea> |
Subtract the immediate data from the destination operand. The immediate data must be in the range 1 to 8. |
|
SUBX |
SUBX Dx,Dy SUBX -(Ax),-(Ay) |
Subtract the source operand from the destination operand along with the extend bit, and store the result in the destination location. |
|
SWAP |
SWAP Dn |
Exchange the upper and lower 16-bit words of a data register. |
|
TAS |
TAS <ea> |
Test and set the byte operand addressed by the effective address field. |
|
TRAP |
TRAP #<vector> |
Force the processor to initiate exception processing. |
|
TRAPV |
TRAPV |
If the V-bit in the CCR is set, then initiate exception processing. |
|
TST |
TST <ea> |
The operand is compared with zero. |
|
UNLK |
UNLK An |
The stack pointer is loaded from the specified address register and the old contents of the stack pointer are lost. |
|
| ||